/* ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. *//** * @file STM32/can_lld.h * @brief STM32 CAN subsystem low level driver header. * * @addtogroup CAN * @{ */#ifndef _CAN_LLD_H_#define _CAN_LLD_H_#if HAL_USE_CAN || defined(__DOXYGEN__)/*===========================================================================*//* Driver constants. *//*===========================================================================*//* * The following macros from the ST header file are replaced with better * equivalents. */#undef CAN_BTR_BRP#undef CAN_BTR_TS1#undef CAN_BTR_TS2#undef CAN_BTR_SJW/** * @brief This switch defines whether the driver implementation supports * a low power switch mode with automatic an wakeup feature. */#define CAN_SUPPORTS_SLEEP TRUE/** * @brief This implementation supports three transmit mailboxes. */#define CAN_TX_MAILBOXES 3/** * @brief This implementation supports two receive mailboxes. */#define CAN_RX_MAILBOXES 2/** * @name CAN registers helper macros * @{ */#define CAN_BTR_BRP(n) (n) /**< @brief BRP field macro.*/#define CAN_BTR_TS1(n) ((n) << 16) /**< @brief TS1 field macro.*/#define CAN_BTR_TS2(n) ((n) << 20) /**< @brief TS2 field macro.*/#define CAN_BTR_SJW(n) ((n) << 24) /**< @brief SJW field macro.*/#define CAN_IDE_STD 0 /**< @brief Standard id. */#define CAN_IDE_EXT 1 /**< @brief Extended id. */#define CAN_RTR_DATA 0 /**< @brief Data frame. */#define CAN_RTR_REMOTE 1 /**< @brief Remote frame. *//** @} *//*===========================================================================*//* Driver pre-compile time settings. *//*===========================================================================*//** * @name Configuration options * @{ *//** * @brief CAN1 driver enable switch. * @details If set to @p TRUE the support for CAN1 is included. */#if !defined(STM32_CAN_USE_CAN1) || defined(__DOXYGEN__)#define STM32_CAN_USE_CAN1 FALSE#endif/** * @brief CAN2 driver enable switch. * @details If set to @p TRUE the support for CAN2 is included. */#if !defined(STM32_CAN_USE_CAN2) || defined(__DOXYGEN__)#define STM32_CAN_USE_CAN2 FALSE#endif/** * @brief CAN1 interrupt priority level setting. */#if !defined(STM32_CAN_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__)#define STM32_CAN_CAN1_IRQ_PRIORITY 11#endif/** @} *//** * @brief CAN2 interrupt priority level setting. */#if !defined(STM32_CAN_CAN2_IRQ_PRIORITY) || defined(__DOXYGEN__)#define STM32_CAN_CAN2_IRQ_PRIORITY 11#endif/** @} *//*===========================================================================*//* Derived constants and error checks. *//*===========================================================================*/#if STM32_CAN_USE_CAN1 && !STM32_HAS_CAN1#error "CAN1 not present in the selected device"#endif#if STM32_CAN_USE_CAN2 && !STM32_HAS_CAN2#error "CAN2 not present in the selected device"#endif#if !STM32_CAN_USE_CAN1 && !STM32_CAN_USE_CAN2#error "CAN driver activated but no CAN peripheral assigned"#endif#if !STM32_CAN_USE_CAN1 && STM32_CAN_USE_CAN2#error "CAN2 requires CAN1, it cannot operate independently"#endif#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP#error "CAN sleep mode not supported in this architecture"#endif/*===========================================================================*//* Driver data structures and types. *//*===========================================================================*//** * @brief Type of a transmission mailbox index. */typedef uint32_t canmbx_t;/** * @brief CAN transmission frame. * @note Accessing the frame data as word16 or word32 is not portable because * machine data endianness, it can be still useful for a quick filling. */typedef struct{ struct { uint8_t DLC:4; /**< @brief Data length. */ uint8_t RTR:1; /**< @brief Frame type. */ uint8_t IDE:1; /**< @brief Identifier type. */ }; union { struct { uint32_t SID:11; /**< @brief Standard identifier.*/ }; struct { uint32_t EID:29; /**< @brief Extended identifier.*/ }; }; union { uint8_t data8[8]; /**< @brief Frame data. */ uint16_t data16[4]; /**< @brief Frame data. */ uint32_t data32[2]; /**< @brief Frame data. */ };}CANTxFrame;/** * @brief CAN received frame. * @note Accessing the frame data as word16 or word32 is not portable because * machine data endianness, it can be still useful for a quick filling. */typedef struct{ struct { uint8_t FMI; /**< @brief Filter id. */ uint16_t TIME; /**< @brief Time stamp. */ }; struct { uint8_t DLC:4; /**< @brief Data length. */ uint8_t RTR:1; /**< @brief Frame type. */ uint8_t IDE:1; /**< @brief Identifier type. */ }; union { struct { uint32_t SID:11; /**< @brief Standard identifier.*/ }; struct { uint32_t EID:29; /**< @brief Extended identifier.*/ }; }; union { uint8_t data8[8]; /**< @brief Frame data. */ uint16_t data16[4]; /**< @brief Frame data. */ uint32_t data32[2]; /**< @brief Frame data. */ };}CANRxFrame;/** * @brief CAN filter. * @note Refer to the STM32 reference manual for info about filters. */typedef struct{ /** * @brief Number of the filter to be programmed. */ uint32_t filter; /** * @brief Filter mode. * @note This bit represent the CAN_FM1R register bit associated to this * filter (0=mask mode, 1=list mode). */ uint32_t mode:1; /** * @brief Filter scale. * @note This bit represent the CAN_FS1R register bit associated to this * filter (0=16 bits mode, 1=32 bits mode). */ uint32_t scale:1; /** * @brief Filter mode. * @note This bit represent the CAN_FFA1R register bit associated to this * filter, must be set to zero in this version of the driver. */ uint32_t assignment:1; /** * @brief Filter register 1 (identifier). */ uint32_t register1; /** * @brief Filter register 2 (mask/identifier depending on mode=0/1). */ uint32_t register2;}CANFilter;/** * @brief Driver configuration structure. */typedef struct{ /** * @brief CAN MCR register initialization data. * @note Some bits in this register are enforced by the driver regardless * their status in this field. */ uint32_t mcr; /** * @brief CAN BTR register initialization data. * @note Some bits in this register are enforced by the driver regardless * their status in this field. */ uint32_t btr;}CANConfig;/** * @brief Structure representing an CAN driver. */typedef struct{ /** * @brief Driver state. */ canstate_t state; /** * @brief Current configuration data. */ const CANConfig *config; /** * @brief Transmission threads queue. */ threads_queue_t txqueue; /** * @brief Receive threads queue. */ threads_queue_t rxqueue; /** * @brief One or more frames become available. * @note After broadcasting this event it will not be broadcasted again * until the received frames queue has been completely emptied. It * is not broadcasted for each received frame. It is * responsibility of the application to empty the queue by * repeatedly invoking @p chReceive() when listening to this event. * This behavior minimizes the interrupt served by the system * because CAN traffic. * @note The flags associated to the listeners will indicate which * receive mailboxes become non-empty. */ event_source_t rxfull_event; /** * @brief One or more transmission mailbox become available. * @note The flags associated to the listeners will indicate which * transmit mailboxes become empty. * */ event_source_t txempty_event; /** * @brief A CAN bus error happened. * @note The flags associated to the listeners will indicate the * error(s) that have occurred. */ event_source_t error_event;#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__) /** * @brief Entering sleep state event. */ event_source_t sleep_event; /** * @brief Exiting sleep state event. */ event_source_t wakeup_event;#endif /* CAN_USE_SLEEP_MODE */ /* End of the mandatory fields.*/ /** * @brief Pointer to the CAN registers. */ CAN_TypeDef *can;}CANDriver;/*===========================================================================*//* Driver macros. *//*===========================================================================*//*===========================================================================*//* External declarations. *//*===========================================================================*/#if STM32_CAN_USE_CAN1 && !defined(__DOXYGEN__)extern CANDriver CAND1;#endif#if STM32_CAN_USE_CAN2 && !defined(__DOXYGEN__)extern CANDriver CAND2;#endif#ifdef __cplusplusextern "C"{ #endif void can_lld_init(void); void can_lld_start(CANDriver *canp); void can_lld_stop(CANDriver *canp); bool can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox); void can_lld_transmit(CANDriver *canp, canmbx_t mailbox, const CANTxFrame *crfp); bool can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox); void can_lld_receive(CANDriver *canp, canmbx_t mailbox, CANRxFrame *ctfp);#if CAN_USE_SLEEP_MODE void can_lld_sleep(CANDriver *canp); void can_lld_wakeup(CANDriver *canp);#endif /* CAN_USE_SLEEP_MODE */ void canSTM32SetFilters(uint32_t can2sb, uint32_t num, const CANFilter *cfp);#ifdef __cplusplus}#endif#endif /* HAL_USE_CAN */#endif /* _CAN_LLD_H_ *//** @} */ /* ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. *//** * @file STM32/can_lld.c * @brief STM32 CAN subsystem low level driver source. * * @addtogroup CAN * @{ */#include "hal.h"#if HAL_USE_CAN || defined(__DOXYGEN__)/*===========================================================================*//* Driver local definitions. *//*===========================================================================*//* * Addressing differences in the headers, they seem unable to agree on names. */#if STM32_CAN_USE_CAN1#if !defined(CAN1)#define CAN1 CAN#endif#endif/*===========================================================================*//* Driver exported variables. *//*===========================================================================*//** @brief CAN1 driver identifier.*/#if STM32_CAN_USE_CAN1 || defined(__DOXYGEN__)CANDriver CAND1;#endif/** @brief CAN2 driver identifier.*/#if STM32_CAN_USE_CAN2 || defined(__DOXYGEN__)CANDriver CAND2;#endif/*===========================================================================*//* Driver local variables and types. *//*===========================================================================*//*===========================================================================*//* Driver local functions. *//*===========================================================================*//** * @brief Programs the filters. * * @param[in] can2sb number of the first filter assigned to CAN2 * @param[in] num number of entries in the filters array, if zero then * a default filter is programmed * @param[in] cfp pointer to the filters array, can be @p NULL if * (num == 0) * * @notapi */static void can_lld_set_filters(uint32_t can2sb, uint32_t num, const CANFilter *cfp){ /* Temporarily enabling CAN1 clock.*/ rccEnableCAN1(FALSE); /* Filters initialization.*/ CAN1->FMR = (CAN1->FMR & 0xFFFF0000) | (can2sb << 8) | CAN_FMR_FINIT; if (num > 0) { uint32_t i, fmask; /* All filters cleared.*/ CAN1->FA1R = 0; CAN1->FM1R = 0; CAN1->FS1R = 0; CAN1->FFA1R = 0; for (i = 0; i < STM32_CAN_MAX_FILTERS; i++) { CAN1->sFilterRegister[i].FR1 = 0; CAN1->sFilterRegister[i].FR2 = 0; } /* Scanning the filters array.*/ for (i = 0; i < num; i++) { fmask = 1 << cfp->filter; if (cfp->mode) CAN1->FM1R |= fmask; if (cfp->scale) CAN1->FS1R |= fmask; if (cfp->assignment) CAN1->FFA1R |= fmask; CAN1->sFilterRegister[cfp->filter].FR1 = cfp->register1; CAN1->sFilterRegister[cfp->filter].FR2 = cfp->register2; CAN1->FA1R |= fmask; cfp++; } } else { /* Setting up a single default filter that enables everything for both CANs.*/ CAN1->sFilterRegister[0].FR1 = 0; CAN1->sFilterRegister[0].FR2 = 0;#if STM32_HAS_CAN2 CAN1->sFilterRegister[can2sb].FR1 = 0; CAN1->sFilterRegister[can2sb].FR2 = 0;#endif CAN1->FM1R = 0; CAN1->FFA1R = 0;#if STM32_HAS_CAN2 CAN1->FS1R = 1 | (1 << can2sb); CAN1->FA1R = 1 | (1 << can2sb);#else CAN1->FS1R = 1; CAN1->FA1R = 1;#endif } CAN1->FMR &= ~CAN_FMR_FINIT; /* Clock disabled, it will be enabled again in can_lld_start().*/ rccDisableCAN1(FALSE);}/** * @brief Common TX ISR handler. * * @param[in] canp pointer to the @p CANDriver object * * @notapi */static void can_lld_tx_handler(CANDriver *canp){ /* No more events until a message is transmitted.*/ canp->can->TSR = CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2; osalSysLockFromISR(); osalThreadDequeueAllI(&canp->txqueue, MSG_OK); osalEventBroadcastFlagsI(&canp->txempty_event, CAN_MAILBOX_TO_MASK(1)); osalSysUnlockFromISR();}/** * @brief Common RX0 ISR handler. * * @param[in] canp pointer to the @p CANDriver object * * @notapi */static void can_lld_rx0_handler(CANDriver *canp){ uint32_t rf0r; rf0r = canp->can->RF0R; if ((rf0r & CAN_RF0R_FMP0) > 0) { /* No more receive events until the queue 0 has been emptied.*/ canp->can->IER &= ~CAN_IER_FMPIE0; osalSysLockFromISR(); osalThreadDequeueAllI(&canp->rxqueue, MSG_OK); osalEventBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(1)); osalSysUnlockFromISR(); } if ((rf0r & CAN_RF0R_FOVR0) > 0) { /* Overflow events handling.*/ canp->can->RF0R = CAN_RF0R_FOVR0; osalSysLockFromISR(); osalEventBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR); osalSysUnlockFromISR(); }}/** * @brief Common RX1 ISR handler. * * @param[in] canp pointer to the @p CANDriver object * * @notapi */static void can_lld_rx1_handler(CANDriver *canp){ uint32_t rf1r; rf1r = canp->can->RF1R; if ((rf1r & CAN_RF1R_FMP1) > 0) { /* No more receive events until the queue 0 has been emptied.*/ canp->can->IER &= ~CAN_IER_FMPIE1; osalSysLockFromISR(); osalThreadDequeueAllI(&canp->rxqueue, MSG_OK); osalEventBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(2)); osalSysUnlockFromISR(); } if ((rf1r & CAN_RF1R_FOVR1) > 0) { /* Overflow events handling.*/ canp->can->RF1R = CAN_RF1R_FOVR1; osalSysLockFromISR(); osalEventBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR); osalSysUnlockFromISR(); }}/** * @brief Common SCE ISR handler. * * @param[in] canp pointer to the @p CANDriver object * * @notapi */static void can_lld_sce_handler(CANDriver *canp){ uint32_t msr; msr = canp->can->MSR; canp->can->MSR = CAN_MSR_ERRI | CAN_MSR_WKUI | CAN_MSR_SLAKI; /* Wakeup event.*/#if CAN_USE_SLEEP_MODE if (msr & CAN_MSR_WKUI) { canp->state = CAN_READY; canp->can->MCR &= ~CAN_MCR_SLEEP; osalSysLockFromISR(); osalEventBroadcastFlagsI(&canp->wakeup_event, 0); osalSysUnlockFromISR(); }#endif /* CAN_USE_SLEEP_MODE */ /* Error event.*/ if (msr & CAN_MSR_ERRI) { eventflags_t flags; uint32_t esr = canp->can->ESR; canp->can->ESR &= ~CAN_ESR_LEC; flags = (eventflags_t)(esr & 7); if ((esr & CAN_ESR_LEC) > 0) flags |= CAN_FRAMING_ERROR; osalSysLockFromISR(); /* The content of the ESR register is copied unchanged in the upper half word of the listener flags mask.*/ osalEventBroadcastFlagsI(&canp->error_event, flags | (eventflags_t)(esr << 16)); osalSysUnlockFromISR(); }}/*===========================================================================*//* Driver interrupt handlers. *//*===========================================================================*/#if STM32_CAN_USE_CAN1 || defined(__DOXYGEN__)#if defined(STM32_CAN1_UNIFIED_HANDLER)/** * @brief CAN1 unified interrupt handler. * * @isr */OSAL_IRQ_HANDLER(STM32_CAN1_UNIFIED_HANDLER){ OSAL_IRQ_PROLOGUE(); can_lld_tx_handler(&CAND1); can_lld_rx0_handler(&CAND1); can_lld_rx1_handler(&CAND1); can_lld_sce_handler(&CAND1); OSAL_IRQ_EPILOGUE();}#else /* !defined(STM32_CAN1_UNIFIED_HANDLER) */#if !defined(STM32_CAN1_TX_HANDLER)#error "STM32_CAN1_TX_HANDLER not defined"#endif#if !defined(STM32_CAN1_RX0_HANDLER)#error "STM32_CAN1_RX0_HANDLER not defined"#endif#if !defined(STM32_CAN1_RX1_HANDLER)#error "STM32_CAN1_RX1_HANDLER not defined"#endif#if !defined(STM32_CAN1_SCE_HANDLER)#error "STM32_CAN1_SCE_HANDLER not defined"#endif/** * @brief CAN1 TX interrupt handler. * * @isr */OSAL_IRQ_HANDLER(STM32_CAN1_TX_HANDLER){ OSAL_IRQ_PROLOGUE(); can_lld_tx_handler(&CAND1); OSAL_IRQ_EPILOGUE();}/* * @brief CAN1 RX0 interrupt handler. * * @isr */OSAL_IRQ_HANDLER(STM32_CAN1_RX0_HANDLER){ OSAL_IRQ_PROLOGUE(); can_lld_rx0_handler(&CAND1); OSAL_IRQ_EPILOGUE();}/** * @brief CAN1 RX1 interrupt handler. * * @isr */OSAL_IRQ_HANDLER(STM32_CAN1_RX1_HANDLER){ OSAL_IRQ_PROLOGUE(); can_lld_rx1_handler(&CAND1); OSAL_IRQ_EPILOGUE();}/** * @brief CAN1 SCE interrupt handler. * * @isr */OSAL_IRQ_HANDLER(STM32_CAN1_SCE_HANDLER){ OSAL_IRQ_PROLOGUE(); can_lld_sce_handler(&CAND1); OSAL_IRQ_EPILOGUE();}#endif /* !defined(STM32_CAN1_UNIFIED_HANDLER) */#endif /* STM32_CAN_USE_CAN1 */#if STM32_CAN_USE_CAN2 || defined(__DOXYGEN__)#if defined(STM32_CAN2_UNIFIED_HANDLER)/** * @brief CAN1 unified interrupt handler. * * @isr */OSAL_IRQ_HANDLER(STM32_CAN2_UNIFIED_HANDLER){ OSAL_IRQ_PROLOGUE(); can_lld_tx_handler(&CAND2); can_lld_rx0_handler(&CAND2); can_lld_rx1_handler(&CAND2); can_lld_sce_handler(&CAND2); OSAL_IRQ_EPILOGUE();}#else /* !defined(STM32_CAN2_UNIFIED_HANDLER) */#if !defined(STM32_CAN1_TX_HANDLER)#error "STM32_CAN1_TX_HANDLER not defined"#endif#if !defined(STM32_CAN1_RX0_HANDLER)#error "STM32_CAN1_RX0_HANDLER not defined"#endif#if !defined(STM32_CAN1_RX1_HANDLER)#error "STM32_CAN1_RX1_HANDLER not defined"#endif#if !defined(STM32_CAN1_SCE_HANDLER)#error "STM32_CAN1_SCE_HANDLER not defined"#endif/** * @brief CAN2 TX interrupt handler. * * @isr */OSAL_IRQ_HANDLER(STM32_CAN2_TX_HANDLER){ OSAL_IRQ_PROLOGUE(); can_lld_tx_handler(&CAND2); OSAL_IRQ_EPILOGUE();}/* * @brief CAN2 RX0 interrupt handler. * * @isr */OSAL_IRQ_HANDLER(STM32_CAN2_RX0_HANDLER){ OSAL_IRQ_PROLOGUE(); can_lld_rx0_handler(&CAND2); OSAL_IRQ_EPILOGUE();}/** * @brief CAN2 RX1 interrupt handler. * * @isr */OSAL_IRQ_HANDLER(STM32_CAN2_RX1_HANDLER){ OSAL_IRQ_PROLOGUE(); can_lld_rx1_handler(&CAND2); OSAL_IRQ_EPILOGUE();}/** * @brief CAN2 SCE interrupt handler. * * @isr */OSAL_IRQ_HANDLER(STM32_CAN2_SCE_HANDLER){ OSAL_IRQ_PROLOGUE(); can_lld_sce_handler(&CAND2); OSAL_IRQ_EPILOGUE();}#endif /* !defined(STM32_CAN2_UNIFIED_HANDLER) */#endif /* STM32_CAN_USE_CAN2 *//*===========================================================================*//* Driver exported functions. *//*===========================================================================*//** * @brief Low level CAN driver initialization. * * @notapi */void can_lld_init(void){ #if STM32_CAN_USE_CAN1 /* Driver initialization.*/ canObjectInit(&CAND1); CAND1.can = CAN1;#endif#if STM32_CAN_USE_CAN2 /* Driver initialization.*/ canObjectInit(&CAND2); CAND2.can = CAN2;#endif /* Filters initialization.*/#if STM32_HAS_CAN2 can_lld_set_filters(STM32_CAN_MAX_FILTERS / 2, 0, NULL);#else can_lld_set_filters(STM32_CAN_MAX_FILTERS, 0, NULL);#endif}/** * @brief Configures and activates the CAN peripheral. * * @param[in] canp pointer to the @p CANDriver object * * @notapi */void can_lld_start(CANDriver *canp){ /* Clock activation.*/#if STM32_CAN_USE_CAN1 if (&CAND1 == canp) { #if defined(STM32_CAN1_UNIFIED_NUMBER) nvicEnableVector(STM32_CAN1_UNIFIED_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);#else nvicEnableVector(STM32_CAN1_TX_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY); nvicEnableVector(STM32_CAN1_RX0_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY); nvicEnableVector(STM32_CAN1_RX1_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY); nvicEnableVector(STM32_CAN1_SCE_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);#endif rccEnableCAN1(FALSE); }#endif#if STM32_CAN_USE_CAN2 if (&CAND2 == canp) { osalDbgAssert(CAND1.state != CAN_STOP, "CAN1 must be started");#if defined(STM32_CAN2_UNIFIED_NUMBER) nvicEnableVector(STM32_CAN2_UNIFIED_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);#else nvicEnableVector(STM32_CAN2_TX_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY); nvicEnableVector(STM32_CAN2_RX0_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY); nvicEnableVector(STM32_CAN2_RX1_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY); nvicEnableVector(STM32_CAN2_SCE_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);#endif rccEnableCAN2(FALSE); }#endif /* Configuring CAN. */ canp->can->MCR = CAN_MCR_INRQ; while ((canp->can->MSR & CAN_MSR_INAK) == 0) osalThreadSleepS(1); canp->can->BTR = canp->config->btr; canp->can->MCR = canp->config->mcr; /* Interrupt sources initialization.*/ canp->can->IER = CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_FMPIE1 | CAN_IER_WKUIE | CAN_IER_ERRIE | CAN_IER_LECIE | CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE | CAN_IER_FOVIE0 | CAN_IER_FOVIE1;}/** * @brief Deactivates the CAN peripheral. * * @param[in] canp pointer to the @p CANDriver object * * @notapi */void can_lld_stop(CANDriver *canp){ /* If in ready state then disables the CAN peripheral.*/ if (canp->state == CAN_READY) { #if STM32_CAN_USE_CAN1 if (&CAND1 == canp) { #if STM32_CAN_USE_CAN2 osalDbgAssert(CAND2.state == CAN_STOP, "CAN2 must be stopped");#endif CAN1->MCR = 0x00010002; /* Register reset value. */ CAN1->IER = 0x00000000; /* All sources disabled. */#if defined(STM32_CAN1_UNIFIED_NUMBER) nvicDisableVector(STM32_CAN1_UNIFIED_NUMBER);#else nvicDisableVector(STM32_CAN1_TX_NUMBER); nvicDisableVector(STM32_CAN1_RX0_NUMBER); nvicDisableVector(STM32_CAN1_RX1_NUMBER); nvicDisableVector(STM32_CAN1_SCE_NUMBER);#endif rccDisableCAN1(FALSE); }#endif#if STM32_CAN_USE_CAN2 if (&CAND2 == canp) { CAN2->MCR = 0x00010002; /* Register reset value. */ CAN2->IER = 0x00000000; /* All sources disabled. */#if defined(STM32_CAN2_UNIFIED_NUMBER) nvicDisableVector(STM32_CAN2_UNIFIED_NUMBER);#else nvicDisableVector(STM32_CAN2_TX_NUMBER); nvicDisableVector(STM32_CAN2_RX0_NUMBER); nvicDisableVector(STM32_CAN2_RX1_NUMBER); nvicDisableVector(STM32_CAN2_SCE_NUMBER);#endif rccDisableCAN2(FALSE); }#endif }}/** * @brief Determines whether a frame can be transmitted. * * @param[in] canp pointer to the @p CANDriver object * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox * * @return The queue space availability. * @retval FALSE no space in the transmit queue. * @retval TRUE transmit slot available. * * @notapi */bool can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox){ switch (mailbox) { case CAN_ANY_MAILBOX: return (canp->can->TSR & CAN_TSR_TME) != 0; case 1: return (canp->can->TSR & CAN_TSR_TME0) != 0; case 2: return (canp->can->TSR & CAN_TSR_TME1) != 0; case 3: return (canp->can->TSR & CAN_TSR_TME2) != 0; default: return FALSE; }}/** * @brief Inserts a frame into the transmit queue. * * @param[in] canp pointer to the @p CANDriver object * @param[in] ctfp pointer to the CAN frame to be transmitted * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox * * @notapi */void can_lld_transmit(CANDriver *canp, canmbx_t mailbox, const CANTxFrame *ctfp){ uint32_t tir; CAN_TxMailBox_TypeDef *tmbp; /* Pointer to a free transmission mailbox.*/ switch (mailbox) { case CAN_ANY_MAILBOX: tmbp = &canp->can->sTxMailBox[(canp->can->TSR & CAN_TSR_CODE) >> 24]; break; case 1: tmbp = &canp->can->sTxMailBox[0]; break; case 2: tmbp = &canp->can->sTxMailBox[1]; break; case 3: tmbp = &canp->can->sTxMailBox[2]; break; default: return; } /* Preparing the message.*/ if (ctfp->IDE) tir = ((uint32_t)ctfp->EID << 3) | ((uint32_t)ctfp->RTR << 1) | CAN_TI0R_IDE; else tir = ((uint32_t)ctfp->SID << 21) | ((uint32_t)ctfp->RTR << 1); tmbp->TDTR = ctfp->DLC; tmbp->TDLR = ctfp->data32[0]; tmbp->TDHR = ctfp->data32[1]; tmbp->TIR = tir | CAN_TI0R_TXRQ;}/** * @brief Determines whether a frame has been received. * * @param[in] canp pointer to the @p CANDriver object * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox * * @return The queue space availability. * @retval FALSE no space in the transmit queue. * @retval TRUE transmit slot available. * * @notapi */bool can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox){ switch (mailbox) { case CAN_ANY_MAILBOX: return ((canp->can->RF0R & CAN_RF0R_FMP0) != 0 || (canp->can->RF1R & CAN_RF1R_FMP1) != 0); case 1: return (canp->can->RF0R & CAN_RF0R_FMP0) != 0; case 2: return (canp->can->RF1R & CAN_RF1R_FMP1) != 0; default: return FALSE; }}/** * @brief Receives a frame from the input queue. * * @param[in] canp pointer to the @p CANDriver object * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox * @param[out] crfp pointer to the buffer where the CAN frame is copied * * @notapi */void can_lld_receive(CANDriver *canp, canmbx_t mailbox, CANRxFrame *crfp){ uint32_t rir, rdtr; if (mailbox == CAN_ANY_MAILBOX) { if ((canp->can->RF0R & CAN_RF0R_FMP0) != 0) mailbox = 1; else if ((canp->can->RF1R & CAN_RF1R_FMP1) != 0) mailbox = 2; else { /* Should not happen, do nothing.*/ return; } } switch (mailbox) { case 1: /* Fetches the message.*/ rir = canp->can->sFIFOMailBox[0].RIR; rdtr = canp->can->sFIFOMailBox[0].RDTR; crfp->data32[0] = canp->can->sFIFOMailBox[0].RDLR; crfp->data32[1] = canp->can->sFIFOMailBox[0].RDHR; /* Releases the mailbox.*/ canp->can->RF0R = CAN_RF0R_RFOM0; /* If the queue is empty re-enables the interrupt in order to generate events again.*/ if ((canp->can->RF0R & CAN_RF0R_FMP0) == 0) canp->can->IER |= CAN_IER_FMPIE0; break; case 2: /* Fetches the message.*/ rir = canp->can->sFIFOMailBox[1].RIR; rdtr = canp->can->sFIFOMailBox[1].RDTR; crfp->data32[0] = canp->can->sFIFOMailBox[1].RDLR; crfp->data32[1] = canp->can->sFIFOMailBox[1].RDHR; /* Releases the mailbox.*/ canp->can->RF1R = CAN_RF1R_RFOM1; /* If the queue is empty re-enables the interrupt in order to generate events again.*/ if ((canp->can->RF1R & CAN_RF1R_FMP1) == 0) canp->can->IER |= CAN_IER_FMPIE1; break; default: /* Should not happen, do nothing.*/ return; } /* Decodes the various fields in the RX frame.*/ crfp->RTR = (rir & CAN_RI0R_RTR) >> 1; crfp->IDE = (rir & CAN_RI0R_IDE) >> 2; if (crfp->IDE) crfp->EID = rir >> 3; else crfp->SID = rir >> 21; crfp->DLC = rdtr & CAN_RDT0R_DLC; crfp->FMI = (uint8_t)(rdtr >> 8); crfp->TIME = (uint16_t)(rdtr >> 16);}#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)/** * @brief Enters the sleep mode. * * @param[in] canp pointer to the @p CANDriver object * * @notapi */void can_lld_sleep(CANDriver *canp){ canp->can->MCR |= CAN_MCR_SLEEP;}/** * @brief Enforces leaving the sleep mode. * * @param[in] canp pointer to the @p CANDriver object * * @notapi */void can_lld_wakeup(CANDriver *canp){ canp->can->MCR &= ~CAN_MCR_SLEEP;}#endif /* CAN_USE_SLEEP_MODE *//** * @brief Programs the filters. * @note This is an STM32-specific API. * * @param[in] can2sb number of the first filter assigned to CAN2 * @param[in] num number of entries in the filters array, if zero then * a default filter is programmed * @param[in] cfp pointer to the filters array, can be @p NULL if * (num == 0) * * @api */void canSTM32SetFilters(uint32_t can2sb, uint32_t num, const CANFilter *cfp){ osalDbgCheck((can2sb >= 1) && (can2sb < STM32_CAN_MAX_FILTERS) && (num <= STM32_CAN_MAX_FILTERS));#if STM32_CAN_USE_CAN1 osalDbgAssert(CAND1.state == CAN_STOP, "invalid state");#endif#if STM32_CAN_USE_CAN2 osalDbgAssert(CAND2.state == CAN_STOP, "invalid state");#endif can_lld_set_filters(can2sb, num, cfp);}#endif /* HAL_USE_CAN *//** @} */